Metal-oxide semiconductor (MOS) devices are generally fabricated by repeated layering of deposited, or grown, and patterned layers that are masked and etched to provide microcircuits. However, minimum feature size requirements (usually determined by resolution of photolithography used in patterning) impose a need for long source and drain regions extending from edges of the gate outward to the field isolation (thick-oxide) layers. Most commonly, source and drain openings are three feature sizes long where one feature size (F) represents the minimum lithography resolution, and is equal to the gate length, as shown in FIG. 1. A conventional MOS device, having a drain area of approximately 3 feature sizes F. is depicted in FIG. 1. It should be noted that the device is fully symmetric. The device includes a gate electrode 10, a lightly doped region 12 of the drain, and a heavily doped region 14 of the drain. There is a thick field oxide 16, a silicide layer 18 and a contact plug 20.
More recently, there are numerous reports in the literature on devices having shorter source and drain openings. These devices reportedly have source-drain openings of 2 feature sizes. Therefore, there is a decreased junction area, and consequently junction capacitance is reduced by approximately 33% when compared to earlier conventional devices. One example is depicted in FIG. 2.
The silicide layer 18, which is used to "metallize" the doped source and drain regions and which is created by the reaction of the deposited metal and the underlying silicon, can only grow within the source-drain openings (on silicon), not on the oxide. An attempt to create a device with source-drain openings 1 feature size long, with the goal of further reducing junction area and capacitance, would cause the contact plugs to land on the oxide (an insulator) and lose contact with the silicide layers, rendering the device inoperable. This is shown in FIG. 3.
The spacing between two contact openings cannot be reduced to less than three feature sizes, because of mask alignment tolerance, which is typically of the order of half of one feature size.
With the advancement of semiconductor technology, devices are being constantly scaled down, with the goal of increasing speed and packing density. The scaling trend is such that all device dimensions are being scaled (reduced) simultaneously by approximately same scaling factor. The depth of source and drain junctions needs to be reduced as well as gate length. However, production of shallow junctions is becoming a problem because of several factors. In a typical manufacturing process, source and drain openings are doped with ion-implantation, a process in which dopant ions are accelerated by an electric field and "shot" into the underlying silicon. In the past, the depth of the implanted profile, and consequently the depth of source and drain junctions, was controlled by acceleration energy. However, as the energy is reduced, the depth of profile does not continue to scale down proportionately with implant energy. Furthermore, as the implant energy is decreased even further, a larger proportion of implanted ions will experience elastic scattering with silicon atoms and simply be bounced back, not entering the silicon. It has been noticed that for low energy implant, a significant fraction of the total implanted dose is stopped in a surface layer, for example, a native oxide film atop of the silicon. This results in dose loss and renders implantation inefficient.
Another problem has to do with the silicide layer. The silicide layer has to have a certain thickness to achieve low resistance path for electric current. On the other hand, the junctions should be as shallow as possible, as this improves certain device characteristics, most notably leakage current in the off-state. Therefore, shallow junctions are needed to improve device characteristics but at the same time, reasonably deep junctions are needed to prevent the growing silicide layer from punching-through the junction, i.e. silicide/silicon interface should not be deeper than the source/drain junction as that would short-circuit the device, rendering it inoperable.
Doped amorphous silicon (a-Si) or poly layer has been widely used in the manufacturing of polysilicon emitter bipolar junction transistors (BJTs) to create shallow junctions for over 20 years. The use of a deposited layer as the dopant source in the creation of MOS device source and drain regions is presented in Georgiou, J. Appl. Phys. 68 (7), 3707 (Oct. 1, 1990). FIG. 4 illustrates the structure of Georgiou, in which an extended region of P-poly 22 reaches from p-type diffusion regions 24 to metal plug connections 26 that connect to aluminum layers 28. As presented in the introduction to Georgiou, the P-poly 22 region is 3500-4000 .ANG. thick. This structure has several limitations. Firstly, the source-drain opening area appears to be limited to 1.5-2 feature sizes, yielding significant junction capacitance and junction leakage when compared to sub 1 feature size devices. Furthermore, the thick polysilicon layer 22 adds resistance to the source and drain because current must flow from region 24 through 3000 .ANG. of polysilicon to reach the silicide 25 on top of layer 22. Source/drain resistance impacts considerably the speed of the device. Furthermore, there is additional significant sidewall capacitance between the gate and source and the gate and drain, as source and drain layers 22 abut the gate 36 for its entire height and are separated by spacer 34. Sidewall capacitance in this device is relatively high. From the drawing by Georgiou, it appears that it is imperative to have a vertically sharply etched field oxide (32) opening. Another disadvantage of the device is that it is not readily producible by current field isolation methods, such as STI or LOCOS.
Although etching is not described in Georgiou, in order to clear the layer 22 on top of the gate 36 and expose the oxide spacers 34 (which then act as boundaries between the silicide on top of the gate and silicide 25 on top of layer 22) a mask is generally required. Furthermore, it is known that addition of lightly doped regions of source drain diffusions under the gate edge has beneficial effects on device performance and MOS devices manufactured today include lightly doped drain extensions (LDDs). The method described by Georgiou does not incorporate LDDs at all.
Providing extremely small diffusion regions with enough dopant atoms to achieve sufficient source/drain concentrations is also a problem at the sub-micron level. Diffusion is accomplished in certain technologies (such as bipolar) by depositing a doped layer of polysilicon (or amorphous silicon) on a substrate and annealing until the sufficient amount of dopants diffuse into the substrate. Control is established by limiting the concentrations of dopant in the surface layer and by controlling the amount of thermal energy supplied in the process. (The thermal energy is controlled by controlling both diffusion temperature and time.) Doping of substrate from a deposited doped layer has not been hitherto applied to CMOS technology, especially not to CMOS devices with LDD structures. Using out-diffusion techniques in sub-micron CMOS devices has not been accomplished in the prior art, due in part to the difficulties in precisely locating (aligning) the doped layer of polysilicon with respect to the gate because of mask misalignment.